[05-17]ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration
Title: ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration
Speaker: 石侃博士（中科院計算所副研究員）
Time: 10:00am, May 17 (Wednesday), 2023.
Venue: 線下：中科院軟件園區5號樓3層計算機科學國家重點實驗室報告廳（334房間）
線上：騰訊會議號：672-379-237
Abstract:
Verification typically consumes the majority of the time in the hardware development cycle. Primarily this is because multiple iterations to debug hardware using software simulation is extremely time-consuming. While FPGAs can be utilised to accelerate the simulation, existing methods either provide limited visibility of design details, or are expensive to check against a reference model dynamically at the system level.
In this talk, I will present ENCORE, an FPGA-accelerated framework for processor architecture verification. The design-under-test (DUT) hardware and the corresponding software emulator run simultaneously on the same FPGA with hardened processors. EN- CORE embodies hardware modules that dynamically monitor and compare key registers from both the DUT and reference model, pausing the execution if any mismatches are detected. In this case, ENCORE automatically creates snapshots of the current design status, and offloads this to software simulators for further debugging. We demonstrate the performance of ENCORE by running RISC-V processor designs and benchmarks. We show that ENCORE can achieve over 44000× speedup over a traditional software simulation-based approach, while maintaining full visibility and debugging capabilities.
Biography:
石侃博士，中科院計算所先進計算系統研究中心副研究員，B站知名 UP主“老石談芯”，主要研究方向：敏捷芯片設計與驗證，FPGA，云數據中心體系結構。博士畢業于倫敦帝國理工學院，曾任英特爾英國研發中心資深芯片設計工程師，兼任英特爾研究院研究科學家。曾獲MICRO Top-Picks論文獎，兩次獲得HiPEAC論文獎，一次最佳論文提名。RISC-V國際基金會技術委員會委員，國際開源硬件組織OpenHW亞洲工作組常委。了解石侃博士的更多信息請訪問https://shilicon.github.io/
